1. Field of Use
This invention pertains to data processing systems and, more particularly, to identification apparatus for transmitting and receiving requests over a common bus.
1. Prior Art
There are a variety of methods and apparatuses for interconnecting the different unit controllers of a data processing system for transmitting and receiving requests over a common bus. The transfer of requests proceeds either over synchronous or asynchronous generated bus transfer cycles of operation.
U.S. Pat. Nos. 4,030,075 and 4,096,569, assigned to the same assignee as named herein, are illustrative of an asynchronous bus system. These systems have units which are coupled in a priority network which is distributed along the system bus.
There are three basic parts to overall sequence of cycles used in communicating along the asynchronous bus network. There is a priority determining part during which the priority network establishes the priority of units wishing to communicate on the bus relative to granting bus cycles. This is followed by a data coming now part during which the highest priority unit is granted access to the bus and is allowed to transfer data, address and command information to the bus. The last part of the sequence is the response part in which a slave unit transmits a response to the requesting device (master unit) indicating its completion of a requested operation.
Read requests include a channel number portion identifying the requestor (i.e., master unit) to permit the response to be directed back to the originator of the request. The master unit compares the channel number portion of each request sent by it to the slave unit during a previous bus cycle with the channel number received back from the slave unit during a subsequent cycle of operation.
Thus, with the exception of memory units identified by memory addresses, each of the units of the system is required to be uniquely identified by a channel number. That is, a unique channel number is assigned to each unit with full and half duplex units being assigned two channel numbers. In such systems, the channel number is set by rotary or thumb wheel switches within the unit. In certain cases, jumpers are included within the unit which are cut to specify the desired channel number.
It has been found that whenever jumpers or switches are required, this raises the factory cost of the unit because of the additional cost for testing the unit's ability to recognize different channel numbers. Also, the reliability of the unit decreases due to the likeliness of incorrect channel number settings. Further, additional documentation is required for instructing how to make channel number assignments.
To overcome the above problems, efforts have been made to assign channel numbers by other than switches or jumpers. Here, it has been observed that when there are no jumpers to define the channel number, the unit will assume some binary number upon being powered up. This introduces into the system the probability that two units could have the same channel number when powered up. Accordingly, when attempts are made to allocate one of these units a specific channel number, both units will assume that channel number. Thus, notwithstanding the type of mechanism used to communicate with the units, the result is that several units have the potential of starting with an incorrect channel number at power-up and being switched to an incorrect channel number value.
Another solution which has been considered is to prewire the channel number of each unit into the back plane of the system bus. The disadvantage is that a considerable number of pins must be allocated for assigning such channel numbers. Also, this can produce other problems where certain units are assigned specific values of channel numbers. For example, processing units in the referenced patents are assigned the first ten channel numbers. When the channel numbers are hardwired into the system, the first ten slots could only be used by processing unit boards and these slots would have to be reserved for such units. Since a system generally has only two processing units, a large number of the slots would remain unused.
In addition to the above, where the channel number is required to be provided by means external to the board, such means cannot be tested by the board itself. Therefore, factory cost is again increased because the board would have to be tried in different slots within the system to verify its allocation of all possible channel number values. The above problems are further complicated where the system has a number of identical units/boards or moreover where the identical units are central processing units.
Accordingly, it is a primary object of the present invention to provide apparatus for reliably ensuring that identical units on a system are assigned unique channel numbers.
It is still a further object of the present invention to provide channel number assignment apparatus which permits the allocation of unique channel numbers to units automatically with a minimum of circuits.